Research Themes (2000.03)

Our laboratory is interested in the researches on fast, area-efficient and low-power system LSI design methods, especially on design autonation and design verification. In other words, desgine methods on high clock frequency, small number of logic elements, and power efficient circuits has been developing.

Reconfigurable Hardware and Its Application

LSI Design and Fabrication

Timing Verification

Events applied to inputs of logic elements are propagated to its outputs with some amount of delays. The delay varies from 10 ps (pico seconds) to 20 ns (nano seconds) depending on the LSI process. In the design, such elements are connected in complex manners, and we should carefully manage the propagation delay for the correct and fast behavior of the cirsuit. We are working on the timing design and verification including the following themes:

Logic Synthesis and Optimization

LSI chips are now designed using hardware description language and then converted gate level circuits using the logic synthesis technologies. We are working on the logic synthesis methods based on local structures on logic circuits. We have worked on the logic function simplification based on local satisfiability don't cares and local observability don't cares, and publised to APCHDL'99 and SASIMI 2000.

Hardware/Software Codesign and Optimization

Information systems are constructed from hardware and software. So systems are usually designed using programming languages such as Java or C language, and then the functionalities of the system are divided into hardware parts and software parts. Especially we can optimize the total system under the so called hardware/ software co-design. We are working on the automatic codesign methods. We have developed a hardware/software codesign environment named GPCP-SS, and a compiler for the GPCP-SS system. We are interested in the data path optimization based on the bit-width estimation of variables used in the system description.

Estimation of Bi Width of Variables in C Programs

In C programs, we use variables with pre-defined types such as the integer, the float, etc., and operations are done on the variables. If the program is processed on a processor, such pre-defined types are efficiently processed. However when generating application specific hardware, we can reduce the hardware area and the delay time by optimizing the bit-width of each variables. We have worked on the automatic estimation for integer variables based on the range computation and obtained 40 % area reduction and 20 % delay reduction after the estimation and we have published the results at IEICE Transactions at Nov. 1999.

Codesign of Video Control Circuits

Real time processing of audio/visual data is one of key applications of application specific hardware. We are working on the codesign environment for such image processing.

Vefirication of Large Circuits

On the hardware implementation, we need a lot of amount of fees and time. If the implementd chip includes bugs, then we need extra fees and time. So the verification of the correctness of the chip design is very important. We are working on the formal design verification based on some mathematical background, such as Boolean algebra, Binary Decision Diagrams (BDD's), and SAT.

Binary Decision Diagrams

Binary decision diagrams (BDD's) are data sturctures representing logic functions, and are widely used in the logic synthesis and verification. We are working on the optimization and parallel processing of BDD's and application to pass-transistor circuit implementations and the results are published at IEICE Transactions at Nov. 1999.

Processor Designs

We are interested in the processor design including application specific circuits, such as network interface and secutiry, etc.
Last modified: 2000.04.01